1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor chip over an insulating substrate.
Priority is claimed on Japanese Patent Application No. 2010-016928, filed Jan. 28, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, with the higher integration of semiconductor chips, miniaturization of wires has progressed, and multi-layered wiring structures have been provided. On the other hand, the package size has to be decreased for more-densely mounting of semiconductor devices. Regarding a semiconductor package, such as a BGA (Ball Grid Array) and a CSP (Chip Size Package), an insulating board and a semiconductor chip on the insulating board are connected by wire-bonding or the like.
Japanese Patent Laid-Open Publication No. 2008-198841 discloses a BGA semiconductor device. Specifically, a wiring board has a rectangular hole in the center region. A semiconductor chip is disposed on the wiring board so as to cover the rectangular hole. Multiple electrode pads are aligned in two lines on the center region of the rear surface of the semiconductor chip. The electrode pads are exposed to the rectangular hole. Multiple connection pads are provided on the rear surface of the wiring board. The connection pads are connected to the electrode pads by wires.
It is easy to connect the electrode pads to the connection pads arranged along one side surface of the hole which is closer to the electrode pads. However, it is difficult to connect the electrode pads to the connection pads arranged along the other side surface of the hole, thereby requiring long wire routing. When the electrode pads are connected using wires to the connection pads arranged along the other side surface of the hole, the distance between the wires and adjacent wires decreases, thereby causing wire a short-circuit when the wires are deformed by flow deformation of a sealing resin and the like.